Hash Joins on Many Core Processors (Intel Xeon Phi)

Modern processor technologies have driven new design and implementation of main-memory hash joins. Recently, Intel Many Integrated Core (MIC) co-processors (commonly known as Xeon Phi) embraces emerging x86 single-chip many-core techniques. Compared with current multi-core CPUs, Xeon Phi has different architectural features: wider SIMD instructions, more cores and hardware contexts, as well as lower-frequency in-order cores.

In this paper, we experimentally revisit the state-of-the-art hash join algorithms on Xeon Phi processors. Particularly, we study two camps of hash join algorithms: hardware-conscious ones, advocating careful tailoring of the join algorithms to underlying hardware architectures, and hardware-oblivious ones, omitting such careful tailoring. For each camp, we study the impact of architectural features and software optimizations on Xeon Phi, in comparison with results on multi-core CPUs. Our experiments show two major findings on Xeon Phi, which are quantitatively different from those on multi-core CPUs. First, the impact of architectural features and software optimizations has quite different behaviour on Xeon Phi, in comparison with those on the CPU. Second, hardware oblivious algorithms can outperform hardware conscious algorithms on a wide parameter window. Those two findings shed light on the design and implementation of query processing on new-generation single-chip many-core technologies.


Source code can be downloaded from here. For setup information and other details stay tuned.


Our code is based on Parallel Join Project at ETHZ


    Submitted to VLDB2014.


  • Saurabh Jha

    Visiting student of Xtra

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